BGDM=0, BRME=0, ABCSE=0, ABCS=0, CKS=00, BCP=000
Common Control Register 2
BCP | Base Clock Pulse 0 (000): 93 clock cycles (S = 93) 1 (001): 128 clock cycles (S = 128) 2 (010): 186 clock cycles (S = 186) 3 (011): 512 clock cycles (S = 512) 4 (100): 32 clock cycles (S = 32) (Initial value) 5 (101): 64 clock cycles (S = 64) 6 (110): 372 clock cycles (S = 372) 7 (111): 256 clock cycles (S = 256) |
BGDM | Baud Rate Generator Double-Speed Mode Select 0 (0): Baud rate generator outputs the clock with single frequency. 1 (1): Baud rate generator outputs the clock with doubled frequency. |
ABCS | Asynchronous Mode Base Clock Select 0 (0): Selects 16 base clock cycles for 1-bit period. 1 (1): Selects 8 base clock cycles for 1-bit period. |
ABCSE | Asynchronous Mode Extended Base Clock Select 0 (0): Clock cycles for 1-bit period is decided with combination be-tween CCR2.BGDM and CCR2.ABCS. 1 (1): Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. |
BRR | Bit rate setting |
BRME | Bit Modulation Enable 0 (0): Bit rate modulation function is disabled. 1 (1): Bit rate modulation function is enabled. |
CKS | Clock Select 0 (00): TCLK clock (n = 0) 1 (01): TCLK/4 clock (n = 1) 2 (10): TCLK/16 clock (n = 2) 3 (11): TCLK/64 clock (n = 3) |
MDDR | Modulation Duty Setting |